1. Technical Field
The present invention generally relates to nonvolatile memory devices, and more particularly, to nonvolatile memory devices and methods of manufacturing the same.
2. Related Art
Researches are being carried out on the next-generation nonvolatile memory devices which do not require a refresh function in order to comply with a need for the lower power of the memory device. A NAND flash memory device, that is, one of the next-generation memory devices, basically includes a memory cell array and a page buffer.
The memory cell array includes a plurality of cells for storing data, a plurality of bit lines, and a plurality of word lines. The plurality of bit lines is connected to respective page buffer circuits.
The page buffer includes the plurality of page buffer circuits. Each of the page buffer circuits includes a bit line selection unit for selecting any one of an even bit line and an odd bit line and a latch unit for latching I/O data and enabling program or reading.
The bit line selection unit of the page buffer circuit commonly includes four NMOS transistors. Each of the NMOS transistors includes a high voltage transistor which can withstand a high voltage. This is because a high voltage of 20 V or higher is used when the erase operation of a common nonvolatile memory device is performed.
The high voltage transistor has a much larger size than a low voltage transistor because it is fabricated so that it can withstand a high voltage. For this reason, the high voltage transistor functions as a limiting factor in reducing the size of a common nonvolatile memory device.